三分频用两个在不同的时钟沿的序列发生器来构成一个3分频信号：
`timescale 1ns/10psmodule div_3(clkin,clkout1,clkout2,clkout3);input clkin;output clkout1,clkout2,clkout3;reg [1:0] step1,step0;always @(posedge clkin)begin case(step0) 2’b00: step0 <= 2’b01; 2’b01: step0 <= 2’b10; 2’b10: step0 <= 2’b00; vps云服务器 default: step0 <= 2’b00; endcaseendalways@(negedge clkin)begin case(step1) 2’b00: step1 <= 2’b01; 2’b01: step1 <= 2’b10; 2’b10: step1 <= 2’b00; default: step1 <= 2’b00;endcaseendassign clkout1 = step0;assign clkout2 = step1;assign clkout3 = ~(step0|step1);endmodule
测试程序如下：
module div_2_tb();reg clkin;wire clkout1,clkout2,clkout3;div_3 wt (.clkin(clkin), .clkout1(clkout1),.clkout2(clkout2),.clkout3(clkout3));initial begin clkin = 0;endalways begin #10 clkin = ~clkin; end endmodule
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